For a long time, a cache is applied in a structure of a processor, so as to relieve a problem of “storage wall” between the processor and a memory, that is, a processing speed of the processor is much greater than a data providing speed of the memory, so that the processor is generally in a “hungry” and waiting state. By using a locality principle of program access, including temporal locality, that is, a storage address being accessed is accessed again in a short period of time, and spatial locality, that is, a certain storage address is accessed, and an adjacent storage address is also accessed within a short period of time, the cache of the processor offsets the speed difference between the processor and the memory, thereby greatly improving performance of the processor. Generally speaking, for most programs, in a given processor structure, a larger cache apparatus always has higher program performance. Therefore, in recent years, the cache of the processor is made larger, and a multi-level cache structure including 2 levels and even 3 levels is also widely used. In a multi-core processor structure, a private cache (used only by a single processor core) and a shared cache (shared by multiple processor cores) are often configured.
However, power consumption of the cache apparatus is greater accordingly, and occupies an increasingly higher proportion in power consumption of a whole processor system, which even reaches 40%-50%. Power consumption is a problem that cannot be ignored in a current processor design field, and over-high power consumption may bring about various problems such as chip heat dissipation and stability problem. Therefore, reducing the power consumption of the cache serving as one of the most important components of the processor may effectively reduce total power consumption of the processor system. However, an existing method for reducing the power consumption of the cache needs support of software, or is at the cost of performance loss, or introduces excessive hardware overheads, thereby increasing complexity in implementation.